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US 2026/0305279 A1Published application
Directly electroplated through-hole via and method
AssigneeRaytheon Company
InventorsAndrew D. Spaeth, Joseph V. Mantese
Life of this patent
Estimating the term…
Abstract
A method includes coupling a wafer including a through-hole to a conductive substrate. The method also includes directly electroplating a through-hole via within the through-hole. The through-hole includes sidewalls formed by the wafer and a base formed by the conductive substrate, and no metallic seed layer is formed between the sidewalls and the through-hole via.
Claims20
A method comprising:
- coupling a wafer comprising a through-hole to a conductive substrate;
- and
- directly electroplating a through-hole via within the through-hole;
- wherein the through-hole comprises sidewalls formed by the wafer and a base formed by the conductive substrate;
- and
- wherein no metallic seed layer is formed between the sidewalls and the through-hole via.
3 more elements
A method comprising:
- forming a through-hole from an upper surface of a wafer to a lower surface of the wafer;
- coupling the wafer to a conductive substrate such that the through-hole comprises sidewalls formed by the wafer and a base formed by the conductive substrate;
- and
- forming a through-hole via within the through-hole, wherein no metallic seed layer is formed between the sidewalls and the through-hole via.
1 more element
A wafer comprising:
- a plurality of directly-electroplated through-hole vias;
- wherein each of the plurality of directly-electroplated through-hole vias is formed within a corresponding through-hole through the wafer;
- and
- wherein, for each directly-electroplated through-hole via, no metallic seed layer is formed between sidewalls of the corresponding through-hole and the directly-electroplated through-hole via.
1 more element
Dependencies are inferred from the claim text.