Bottom electrode structure in memory device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChao-Yang Chen, Chun-Yang Tsai, Kuo-Ching Huang, Wen-Ting Chu, Pili Huang, Cheng-Jun Wu
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChao-Yang Chen, Chun-Yang Tsai, Kuo-Ching Huang, Wen-Ting Chu, Pili Huang, Cheng-Jun Wu
Estimating the term…
In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed over a substrate and including a first material having a first electronegativity. A bottom electrode diffusion barrier surrounds the bottom electrode. A metal oxide and/or a metal oxy-nitride is disposed between the bottom electrode and a top electrode. A conductive layer includes a second material that is disposed directly between the bottom electrode diffusion barrier and the bottom electrode. The second material has a second electronegativity that is greater than the first electronegativity based on Pauling's scale.
An integrated chip, comprising:
An integrated chip, comprising:
An integrated chip, comprising:
Dependencies are inferred from the claim text.