Backside contact with epitaxial liner

A method comprising:

• providing a first transistor comprising first channels and a first source/drain region and a second transistor comprising second channels and a second source/drain region, the first and second channels being over a bottom dielectric isolation layer, wherein the first source/drain region and the second source/drain region extend beyond a bottom surface of the bottom dielectric isolation layer;
• forming a trench-shaped epitaxial liner on the first source/drain region;
• and
• forming backside conductive material in the trench-shaped epitaxial liner.

A semiconductor structure comprising:

• an n-type transistor (NFET) comprising first channels and a first source/drain region and a p-type transistor (PFET) comprising second channels and a second source/drain region, the first and second channels being over a bottom dielectric isolation layer, wherein the first source/drain region and the second source/drain region extend beyond a bottom surface of the bottom dielectric isolation layer;
• a first backside conductive material formed in an n-type trench-shaped epitaxial liner, the n-type trench-shaped epitaxial liner being formed on the first source/drain region;
• and
• a second backside conductive material formed in a p-type trench-shaped epitaxial liner, the p-type trench-shaped epitaxial liner being formed on the second source/drain region.