Monolithic integration of iii-n devices including a conductive layer

A semiconductor device, comprising:

• a substrate;
• a lower III-N stack over the substrate;
• a conductive layer over the lower III-N stack;
• an upper III-N stack over the conductive layer, the upper III-N stack including a channel layer;
• a barrier layer over the channel layer, the barrier layer and the channel layer forming a first heterojunction structure;
• a first III-N transistor disposed over a first area of the substrate, the first III-N transistor including a first source region and a first drain region, wherein a first drain contact is disposed in the first drain region and a first source contact is disposed in the first source region;
• a second III-N transistor disposed over a second area of the substrate, the second area laterally separated from the first area by a first isolation region, the second III-N transistor including a second source region and a second drain region, wherein a second drain contact is disposed in the second drain region and a second source contact disposed in the second source region is connected to the first drain contact of the first III-N transistor;
• and
• a third III-N transistor disposed over a third area of the substrate, the third area laterally separated from the second area by a second isolation region, the third III-N transistor including a third source region and a third drain region, wherein a third source contact disposed in the third source region is coupled to the conductive layer and a third drain contact disposed in the third drain region is connected to the second drain contact of the second III-N transistor, and wherein a third gate contact of the third III-N transistor is connected to a second gate contact of the second III-N transistor.