Semiconductor device including additional gate insulation pattern

A semiconductor device comprising:

• an active area in a substrate;
• a fin structure in the active area and comprising a channel pattern on the active area, a source region, and a drain region;
• a gate electrode on at least a portion of a side surface and an upper surface of the channel pattern of the fin structure;
• a gate insulating layer between the channel pattern and the gate electrode;
• and
• a sloped insulation pattern between the drain and the gate electrode and comprising a slope surface inclined with respect to the channel pattern.

A semiconductor device comprising:

• a substrate;
• an active pattern extending along a first direction on the substrate;
• a first semiconductor pattern and a second semiconductor pattern vertically stacked on the active pattern and spaced apart from each other;
• a gate electrode on the active pattern, extending in a second direction, and surrounding the first semiconductor pattern and the second semiconductor pattern;
• a first source/drain pattern and a second source/drain pattern at least at opposite sides of the gate electrode;
• and
• a sloped insulation pattern between the gate electrode and one of the first source/drain pattern and the second source/drain pattern and inclined with respect to an upper surface of the second semiconductor pattern.