Semiconductor device having nanostructure transistor and methods of fabrication thereof

A semiconductor device structure, comprising:

• a plurality of nanostructure channels stacked over a substrate and spaced apart from one another along a direction perpendicular to a top surface of the substrate;
• a gate structure surrounding each of the plurality of nanostructure channels, the gate structure comprising a gate dielectric layer and a gate electrode layer on the gate dielectric layer;
• a first source/drain epitaxial feature and a second source/drain epitaxial feature over the substrate and on opposite sides of the gate structure, the first and second source/drain epitaxial features being connected by the plurality of nanostructure channels;
• and
• a plurality of dielectric spacers disposed between adjacent nanostructure channels and between the gate structure and the first source/drain epitaxial feature,
• wherein each of the plurality of dielectric spacers has a first surface contacting the gate dielectric layer and a flat second surface facing the first source/drain epitaxial feature, and
• wherein the flat second surface of each of the plurality of dielectric spacers is laterally offset from a sidewall of an adjacent one of the plurality of nanostructure channels by a lateral distance.

A semiconductor device structure, comprising:

• a source/drain epitaxial feature over a substrate;
• a plurality of semiconductor layers stacked over the substrate, each of the plurality of semiconductor layers being in contact with the source/drain epitaxial feature and having a surface portion adjacent the source/drain epitaxial feature, wherein the surface portion comprises a halogen;
• a gate dielectric layer wrapping around each of the plurality of semiconductor layers;
• a gate electrode layer on the gate dielectric layer;
• and
• a dielectric spacer disposed between the gate dielectric layer and the source/drain epitaxial feature and between adjacent ones of the plurality of semiconductor layers.