Ferroelectric memory device with multi-level bit cell

A method of operating a ferroelectric memory device,

• wherein the ferroelectric memory device comprises:
• a fin-shaped active pattern disposed over a substrate and extending in a first direction parallel to a top surface of the substrate, the fin-shaped active pattern including a channel region, a source region, and a drain region;
• and
• a gate structure disposed over the substrate and configured to wrap a top surface and opposite sidewalls of the fin-shaped active pattern,
• wherein the gate structure includes:
• a gate electrode;
• an oxide layer disposed on the channel region of the fin-shaped active pattern;
• and
• a ferroelectric layer disposed between the gate electrode and the oxide layer in a direction perpendicular to the opposite sidewalls of the fin-shaped active pattern,
• wherein the gate structure includes a first gate portion and a second gate portion disposed on the opposite sidewalls of the fin-shaped active pattern, respectively, and
• wherein at least one of the oxide layer and the ferroelectric layer has a first thickness in the first gate portion and a second thickness in the second gate portion, the first thickness being different from the second thickness, and
• wherein the method comprises:
• in order to write a first state, applying a supply voltage to the gate structure and applying a ground voltage to the drain region and the source region;
• in order to write a second state, applying the supply voltage to the drain region and the source region and applying the ground voltage to the gate structure, and then applying a low voltage that is lower than the supply voltage to the gate structure and applying the ground voltage to the drain region and the source region;
• in order to write a third state, applying the supply voltage to the gate structure and applying the ground voltage to the drain region and the source region, and then applying the low voltage to the drain region and the source region and applying the ground voltage to the gate structure;
• and
• in order to write a fourth state, applying the supply voltage to the drain region and the source region and applying the ground voltage to the gate structure.

A memory device including a ferroelectric field effect transistor (FeFET), the FeFET comprising:

• a fin-shaped active pattern disposed over a substrate and extending in a first direction parallel to a top surface of the substrate, the fin-shaped active pattern including a channel region, a source region, and a drain region;
• and
• a gate structure disposed over the substrate and configured to wrap a top surface and opposite sidewalls of the fin-shaped active pattern,
• wherein the gate structure includes:
• a gate electrode;
• an oxide layer disposed on the channel region of the fin-shaped active pattern;
• and
• a ferroelectric layer disposed between the gate electrode and the oxide layer in a direction perpendicular to the opposite sidewalls of the fin-shaped active pattern,
• wherein the gate structure includes a first gate portion and a second gate portion disposed on the opposite sidewalls of the fin-shaped active pattern, respectively,
• wherein at least one of the oxide layer and the ferroelectric layer has a first thickness in the first gate portion and a second thickness in the second gate portion, the first thickness being different from the second thickness,
• wherein the FeFET includes a first storage device including the first gate portion and a second storage device including the second gate portion, each storage device being configured to store 1-bit data, so that the FeFET is configured to store 2-bit data.