Semiconductor devices including interconnection patterns

A semiconductor device, comprising:

• a transistor structure;
• a first interconnection structure on the transistor structure;
• and
• a second interconnection structure on the first interconnection structure,
• wherein the first interconnection structure comprises:
• a first interconnection pattern extending in a first direction;
• and
• a first intermetallic insulating layer covering an upper surface of a portion of the transistor structure, an upper surface and side surfaces of the first interconnection pattern, and having a first via hole spaced apart from the first interconnection pattern,
• wherein the second interconnection structure comprises:
• a first conductive via filling the first via hole of the first intermetallic insulating layer;
• a second interconnection pattern disposed on the first intermetallic insulating layer and the first conductive via, extending in a second direction, intersecting the first interconnection pattern, and contacting an upper surface of the first conductive via;
• and
• a second intermetallic insulating layer covering an upper surface of a portion of the first interconnection structure, and side surfaces of the second interconnection pattern,
• wherein a thickness of the first intermetallic insulating layer is greater than a height of the conductive via.

A semiconductor device, comprising:

• a first interconnection pattern on a first level;
• a second interconnection pattern on a second level, higher than the first level;
• conductive vias respectively contacting a lower surface of the second interconnection pattern and disposed between the first level and the second level;
• a fuse via, which is one of the conductive vias and is adjacent to the first interconnection pattern;
• a fuse insulating material between the fuse via and the first interconnection pattern,
• wherein the fuse insulating material is configured such that insulation breakdown occurs when a voltage higher than a critical level is applied between the fuse via and the first interconnection pattern.