Memory device including channel structure
AssigneeSK hynix Inc.
InventorHeon Yong CHANG
Life of this patent
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Abstract
A memory device may include a channel structure including a first end and a second end that is opposite to the first end in a vertical direction; a data storage pattern connected to the first end of the channel structure; a bit line contacting the second end of the channel structure; a bonding insulating layer disposed over the bit line; a first substrate disposed over the bonding insulating layer, and including a first surface that faces the bit line and a second surface that is opposite to the first surface in the vertical direction; and a first transistor disposed on the second surface of the first substrate.
Claims20
A memory device comprising:
- a channel structure including a first end and a second end that is opposite to the first end in a vertical direction;
- a data storage pattern connected to the first end of the channel structure;
- a bit line contacting the second end of the channel structure;
- a bonding insulating layer disposed over the bit line;
- a first substrate disposed over the bonding insulating layer, and including a first surface that faces the bit line and a second surface that is opposite to the first surface in the vertical direction;
- and
- a first transistor disposed on the second surface of the first substrate.
A memory device comprising:
- a first semiconductor structure including a channel structure, a bit line that contacts an upper surface of the channel structure and a first bonding insulating layer over the bit line;
- a second semiconductor structure including a second bonding insulating layer that is bonded to the first bonding insulating layer, a first substrate that is disposed over the second bonding insulating layer and a first transistor that is disposed on the first substrate;
- and
- a plurality of contact plugs, including a first contact plug, a second contact plug and a third contact plug that are spaced apart from each other, that connect the first semiconductor structure and the second semiconductor structure by penetrating through the first substrate, the first bonding insulating layer and the second bonding insulating layer.
A memory device comprising:
- a channel structure including a first end and a second end that is located opposite to the first end in a vertical direction;
- a data storage pattern connected to the first end of the channel structure;
- a bit line contacting the second end of the channel structure;
- a bonding insulating layer located over the bit line;
- a first substrate located over the bonding insulating layer;
- a plurality of wirings located over the first substrate;
- and
- a plurality of contact plugs directly connected to the plurality of wirings, respectively, and penetrating through the bonding insulating layer and the first substrate.
Dependencies are inferred from the claim text.