Memory cell having three-dimensional structure, operating method thereof, and memory device
AssigneeFoundation for Research and Business, Seoul National University of Science and Technology
InventorsWonbo SHIM, Kwangsoo KIM
Life of this patent
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Abstract
A memory cell having a 3D structure, an operating method thereof, and a memory device include a write complementary field effect transistor (CFET) in a gate-all-around (GAA) structure, including a first metal-oxide-semiconductor field-effect transistor (MOSFET) and a second MOSFET, a read CFET in a GAA structure, including a third MOSFET and a fourth MOSFET disposed adjacent in a horizontal direction from the write CFET, and a first connecting metal that forms a storage node by connecting a drain or a source of the first MOSFET and a gate of the read CFET.
Claims20
A memory cell comprising:
- a write complementary field effect transistor (CFET) in a gate-all-around (GAA) structure, comprising a first metal-oxide-semiconductor field-effect transistor (MOSFET) and a second MOSFET;
- a read CFET in a GAA structure, comprising a third MOSFET and a fourth MOSFET disposed adjacent in a horizontal direction from the write CFET;
- and
- a first connecting metal that forms a storage node by connecting a drain or a source of the first MOSFET and a gate of the read CFET.
A memory device comprising:
- a word line configured with each of a plurality of first word lines and a plurality of second word lines;
- a bit line configured with each of a plurality of first bit lines and a plurality of second bit lines;
- and
- a memory cell array configured with a plurality of memory cells, the memory cell comprising a write complementary field effect transistor (CFET) comprising a first metal-oxide-semiconductor field-effect transistor (MOSFET) and a second MOSFET having a source or drain region connected to one of the plurality of first bit lines and comprising a gate connected to one of the plurality of first word lines, a read CFET comprising a third MOSFET having a drain or source region connected to one of the plurality of second word lines and a fourth MOSFET having a source or drain region connected to one of the plurality of second bit lines, in which a storage node is formed by connecting the drain or source region of the first MOSFET or the second MOSFET and a gate of the read CFET.
A memory cell comprising:
- a read complementary field effect transistor (CFET) in a gate-all-around (GAA) structure comprising a first metal-oxide-semiconductor field-effect transistor (MOSFET) and a second MOSFET;
- a write transistor comprising an oxide channel layer and positioned on a first insulating layer which is an upper portion of the read CFET;
- and
- a third connecting metal that forms a storage node by connecting a gate of the read CFET and one of a source or drain region of the write transistor.
Dependencies are inferred from the claim text.