Interlocking Cell-Pair Layout of Buffered Read Port Static Random-Access Memory (SRAM) with P and N Pass Gates to Same Write Bit Line

A 12-transistor cell layout comprising:

• a writable cell having 4 p-channel transistors and 4 n-channel transistors arranged as a cross-coupled pair of inverters and a first transmission gate to a first bit line and a second transmission gate to a second bit line;
• a buffered read port having 2 p-channel transistors and 2 n-channel transistors that include data transistors having gates driven by an inverter in the cross-coupled pair of inverters and select transistors having gates driven by a read select signal, for driving data onto a data line;
• wherein the writable cell is laid out in a first rectangle and the buffered read port is laid out in a second rectangle that abuts the first rectangle;
• wherein two second rectangles fit into a pitch of the first rectangle;
• wherein the first rectangle and the second rectangle form an L-shaped area;
• wherein an even instance of the writable cell is laid out in a first column;
• wherein an even instance of the buffered read port and an odd instance of the buffered read port are laid out in a second column that is adjacent to the first column;
• wherein an odd instance of the writable cell is laid out in a third column that is adjacent to the second column and separated from the first column by the second column, whereby even and odd cell instances of cells having the L-shaped area are laid out in an interlocking pattern.

A Static Random-Access Memory (SRAM) cell comprising:

• a write-only SRAM cell that comprises:
• a first pull-up transistor and a first pull-down transistor connected in series between a power supply and a ground, the first pull-up transistor and the first pull-down transistor connected at a first latch node;
• a second pull-up transistor and a second pull-down transistor connected in series between the power supply and the ground, the second pull-up transistor and the second pull-down transistor connected at a second latch node;
• wherein gates of the first pull-up transistor and of the first pull-down transistor are driven by the second latch node between the second pull-up transistor and the second pull-down transistor;
• wherein gates of the second pull-up transistor and of the second pull-down transistor are driven by the first latch node between the first pull-up transistor and the first pull-down transistor;
• a first n-channel pass transistor connected between the first latch node and a first write bit line, and having a gate connected to a write word line;
• a second n-channel pass transistor connected between the second latch node and a second write bit line, and having a gate connected to the write word line;
• a first p-channel pass transistor connected between the first latch node and the first write bit line, and having a gate connected to an inverse write word line;
• a second p-channel pass transistor connected between the second latch node and the second write bit line, and having a gate connected to the inverse write word line;
• a buffered read port that comprises:
• a buffer transistor with a gate connected to the second latch node from the write-only SRAM cell, and a channel that conducts current controlled by the gate;
• and a pass transistor having a gate connected to a read word line and a channel connected between the channel of the buffer transistor and a read bit line;
• wherein reading is performed by activating the read word line and sensing read data on the read bit line;
• wherein writing is performed by activating the write word line high and the inverse write word line low and driving input data onto the first write bit line and driving an inverse of the input data onto the second write bit line;
• wherein the buffered read port further comprises:
• a p-channel buffer transistor with a gate connected to the second latch node from the write-only SRAM cell, and a channel that conducts current between the power supply and a first read-port node;
• a p-channel pass transistor having a gate connected to an inverse read word line and a channel connected between first read-port node and the read bit line;
• wherein the buffer transistor further comprises a n-channel buffer transistor with the gate connected to the second latch node from the write-only SRAM cell, and the channel that conducts current between the ground and a second read-port node;
• wherein the pass transistor further comprises a n-channel pass transistor having the gate connected to the read word line and the channel connected between the second read-port node and the read bit line;
• wherein two instances of the buffered read port are laid out next to each other between an even instance of the write-only SRAM cell and an odd instance of the write-only SRAM cell;
• wherein an even instance of the buffered read port is con wherein an odd instance of the buffered read port is connected to the second latch node from the odd instance of the write-only SRAM cell;
• whereby a pair of the SRAM cell is laid out as a pair of L-shaped interlocked cells.