Phase error monitor

An apparatus comprising:

• a transmitter (Tx) circuit comprising:
• a Tx output network circuit;
• and
• a slicer circuit comprising a first input terminal coupled to the Tx output network circuit;
• and
• a current symbol identification circuit comprising:
• a data delay circuit comprising an input terminal to receive transmit data supplied to the Tx circuit;
• a multiplier circuit comprising a first input terminal coupled to an output terminal of the slicer circuit and a second input terminal coupled to an output terminal of the data delay circuit;
• and
• an alignment detector circuit comprising an input terminal coupled to an output terminal of the multiplier circuit.

A process of making a phase error monitor, the process comprising:

• coupling a first input terminal of a slicer circuit to a transmitter (Tx) output network circuit;
• coupling an input terminal of a data delay circuit to a terminal providing transmit data;
• coupling a first input terminal of a multiplier circuit to an output terminal of the slicer circuit;
• coupling a second input terminal of the multiplier circuit to an output terminal of the data delay circuit;
• and
• coupling an input terminal of an alignment detector circuit to an output terminal of the multiplier circuit.