System and method for low density parity check (ldpc) code with 5/6 code rate
AssigneeAvago Technologies International Sales Pte. Limited
InventorsRethnakaran Pulikkoonattu, Andrew Blanksby, Vinko Erceg
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AssigneeAvago Technologies International Sales Pte. Limited
InventorsRethnakaran Pulikkoonattu, Andrew Blanksby, Vinko Erceg
Estimating the term…
In some implementations, an apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, according to a code rate of 5/6 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code. The first binary parity check matrix may correspond to a first exponent matrix having 96 values. The one or more processors may be configured to encode data using the first binary parity check matrix. The one or more processors may be configured to transmit the encoded data.
An apparatus comprising:
An apparatus comprising:
A method comprising:
Dependencies are inferred from the claim text.