Balanced monotonic successive approximation adc

Abstract

One illustrative n-bit balanced monotonic SAR ADC includes: a sample and hold element, a first bank of capacitances, a comparator, and control logic. The sample and hold element is coupled to a first sensing node to provide an input voltage. The first bank of capacitances includes: n−1 upper capacitances each having a switchable input node that is initially coupled to an upper reference voltage and is switchable to a lower reference voltage; and n−1 lower capacitances each having a switchable input node that is initially coupled to the lower reference voltage and is switchable to the upper reference voltage. The comparator provides a bit decision signal based on a voltage of a first sensing node. The logic controls switches for the first bank of capacitances based on the bit decision signal, thereby causing the bit decision signal to provide a sequential binary representation of the input voltage.

Dependencies are inferred from the claim text.