Level shift circuit and level shifter
AssigneeAblic Inc.
InventorEiki IMAIZUMI
Life of this patent
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Abstract
In order to enable generating an output logic signal having a duty cycle substantially equal to a duty cycle of an input logic signal, provided is a level shift circuit including a first transistor, a second transistor, a third transistor, a fourth transistor, a clamp circuit for limiting voltages of a first node and a second node within a range from a third voltage to a fourth voltage, and a waveform shaping circuit for providing an output logic signal based on level transitions of an input first logic signal and an input second logic signal in the same direction.
Claims6
A level shift circuit for shifting a level of an input logic signal indicating logic levels with a first voltage and a second voltage into an output logic signal indicating logic levels with a third voltage and a fourth voltage, the level shift circuit comprising:
- a first transistor including a gate supplied with a reverse-phase signal of the input logic signal, a source connected to the first voltage, and a drain connected to a clamp circuit;
- a second transistor including a gate supplied with a positive-phase signal of the input logic signal, a source connected to the first voltage, and a drain connected to the clamp circuit;
- a third transistor including a source connected to the fourth voltage and a drain connected to the clamp circuit;
- a fourth transistor including a source connected to the fourth voltage and a drain connected to the clamp circuit;
- the clamp circuit connected to a first node and a second node and configured to limit voltages of the first node and the second node within a range from the third voltage to the fourth voltage;
- a first buffer circuit configured to receive the voltage of the first node and provide a first logic signal corresponding to the voltage of the first node;
- a second buffer circuit configured to receive the voltage of the second node and provide a second logic signal corresponding to the voltage of the second node;
- and
- a waveform shaping circuit configured to receive the first logic signal and the second logic signal and provide the output logic signal based on level transitions of the first logic signal and the second logic signal in the same direction,
- in which, of a pair of the first transistor and the second transistor and a pair of the third transistor and the fourth transistor, the pair connected to a high-voltage side are of a first conductivity type being one of a P-type or an N-type, and the pair connected to a low-voltage side are of a second conductivity type being another one of the P-type or the N-type.
Dependencies are inferred from the claim text.