Method and device for generating a bus of randomly distributed signals

A method of producing, by at least one processor, an Integrated Circuit (IC), the method comprising:

• calculating an approximation circuit schematic, representing an approximation circuit, adapted to receive one or more first Independent, and Identically Distributed (IID) HB binary signals, and generate therefrom an approximation signal that is binary and randomly distributed;
• calculating one or more complementary schematics, respectively representing one or more complementary circuits, wherein each complementary circuit is configured to receive (i) the approximation signal, and (ii) at least one second IID binary signal, and generate therefrom one or more respective complementary signals that are random and binary;
• calculating an integration schematic, representing an integration circuit, configured to produce a bus of random binary signals, having required, non-binary probabilities, based on the approximation signal and the one or more complementary signals;
• and
• translating said schematics into a physical layout design, utilizable for fabricating the IC.

A system for producing an Integrated Circuit (IC), the system comprising:

• a non-transitory memory device, wherein modules of instruction code are stored, and at least one processor associated with the memory device, and configured to execute the modules of instruction code, whereupon execution of said modules of instruction code, the at least one processor is configured to:
• calculate an approximation circuit schematic, representing an approximation circuit, adapted to receive one or more first Independent, and Identically Distributed (IID) IID binary signals, and generate therefrom an approximation signal that is binary, and randomly distributed;
• calculate one or more complementary schematics, respectively representing one or more complementary circuits, wherein each complementary circuit is configured to receive (i) the approximation signal, and (ii) at least one second IID binary signal, and generate therefrom one or more respective complementary signals that are random and binary;
• calculate an integration schematic, representing an integration circuit, configured to produce a bus of random binary signals, having required, non-binary probabilities, based on the approximation signal and the one or more complementary signals;
• and
• translating said schematics into a physical layout design, utilizable for fabricating the IC.