Complementary clocked storage elements

Abstract

An integrated circuit includes a first flip-flop comprising a first master latch with a first circuit configuration and a first slave latch with a second circuit configuration, and a second flip-flop comprising a second master latch with the second circuit configuration and a second slave latch with the first circuit configuration. Swapping the master and slave roles of the same two circuit configurations causes the first flip-flop to trigger on one clock edge direction and the second flip-flop to trigger on the opposite clock edge direction, both using clock signals of matching polarity without requiring a clock inverter. The circuit configurations may each include a merged OR-NAND or AND-NOR transistor stack with a respective NAND or NOR feedback stack. Independently placeable library cells embodying the two circuit configurations enable flexible placement of the flip-flops and their constituent master and slave latches within an integrated circuit design.

Dependencies are inferred from the claim text.