Clock generation circuit and semiconductor components
AssigneeWinbond Electronics Corp.
InventorYasue Yamamoto
Life of this patent
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Abstract
A clock generation circuit that reduces frequency of a clock signal when a power supply voltage increases. The clock generation circuit of the disclosure includes a reference current setting unit, a bias voltage generation unit, and a ring oscillator. The bias voltage generation unit generates a PBIAS voltage applied to gates of PMOS transistors and an NBIAS voltage applied to gates of NMOS transistors in the ring oscillator. In response to the power supply voltage reaching a target voltage, the bias voltage generation unit increases the PBIAS voltage, thereby reducing a current supplied by the PMOS transistors and lowering frequency of the clock signal.
Claims18
A clock generation circuit, comprising:
- a ring oscillator, having an odd number of inverter stages connected in series, the inverter stages comprising a P-channel metal oxide semiconductor transistor connected between a power supply voltage and a complementary metal oxide semiconductor inverter;
- a generation component, generating a first bias voltage commonly applied to gates of the P-channel metal oxide semiconductor transistors of the ring oscillator;
- and
- a detection component, comprising an operational amplifier detecting an increase of the power supply voltage and a first transistor having a gate connected to an output of the operational amplifier,
- wherein the generation component enlarges the first bias voltage according to a first current flowing through the first transistor.
Dependencies are inferred from the claim text.