Back to results
US 2026/0301849 A1Published application
Memory with Double Redundancy
AssigneeQUALCOMM Incorporated
InventorsKiran DHAMANE, Debarghya DUTTA, Rahul SAHU, Anoop KUMAR
Life of this patent
Estimating the term…
Abstract
A memory is provided with a bank including a plurality of global input/output (GIO) columns and a corresponding plurality of GIO circuits. Each GIO circuit includes a switch matrix. In a no-shift region, the switch matrix couples the GIO circuit to a core in the corresponding GIO column. In a one-shift region, the switch matrix couples the GIOO circuit to a core in a subsequent GIO column. In a two-shift region, the switch matrix couples the GIO circuit to a core in a next-to-subsequent GIO column.
Claims20
A memory, comprising:
- a first global input/output column of bitcells;
- a second global input/output column of bitcells;
- a third global input/output column of bitcells, wherein the first global input/output column, the second global input/output column, and the third global input/output column are arranged in a consecutive order within a first bank;
- a first data output latch;
- and
- a switch matrix including a first switch connected between an output terminal of the first global input/output column and an input terminal of the first data output latch, a second switch connected between an output terminal of the second global input/output column and the input terminal of the first data output latch, and a third switch coupled between an output terminal of the third global input/output column and the input terminal of the first data output latch.
3 more elements
A memory, comprising:
- a first global input/output column of bitcells;
- a second global input/output column of bitcells;
- a third global input/output column of bitcells, wherein the first global input/output column, the second global input/output column, and the third global input/output column are arranged in a consecutive order;
- a first data input latch;
- and
- a first switch matrix having a first switch connected between an output terminal of the first data input latch and an input terminal of the first global input/output column, a second switch connected between the output terminal of the first data input latch and an input terminal of the second global input/output column, and a third switch coupled between the output terminal of the first data input latch and an input terminal of the third global input/output column.
3 more elements
A method of column redundancy, comprising:
- closing a single first switch to connect a first latch to a first global input/output column in a plurality of global input/output columns responsive to a subset of the plurality of global input/output columns that extends from an initial global input/output column to the first global input/output column having no defects;
- closing a single second switch to connect the first latch to a second global input/output column in the plurality of global input/output columns responsive to the first global input/output column including a first defective column, wherein the second global input/output column is adjacent to the first global input/output column;
- and
- closing a single third switch to connect the first latch to a third global input/output column in the plurality of global input/output columns responsive to the second global input/output column including a second defective column, wherein the third global input/output column is adjacent to the second global input/output column.
1 more element
Dependencies are inferred from the claim text.