Dynamic random-access memory (dram) convertible to permanent storage

A dynamic random-access memory (DRAM) comprising:

• an array of bit cells, each bit cell having a corresponding access transistor coupled to a corresponding word line along a corresponding row of the array and a corresponding bit line along a corresponding column of the array, a corresponding storage transistor having a gate electrode coupled to a first current electrode of the corresponding access transistor, a corresponding capacitor having a first terminal coupled to the gate electrode of the storage transistor, and a corresponding diode coupled between a second terminal of the corresponding capacitor and a corresponding voltage supply rail along the corresponding row of the array;
• and
• a controller configured to, for each row of the array:
• apply a first voltage to the corresponding word line along the row of the array to turn on the corresponding access transistors of each of the bit cells along the row of the array, and apply a second voltage to the corresponding voltage supply rail along the row;
• for a set of selected bit cells of the row, apply a third voltage to the corresponding bit line of each of the set of selected bit cells;
• and
• for a set of unselected bit cells of the row, apply a fourth voltage to the corresponding bit line of each of the set of unselected bit cells,
• wherein a differential between the third and second voltage is sufficient to permanently break down a dielectric of the corresponding capacitor of each of the set of selected bit cells such that each of the set of selected bit cells is permanently programmed to a discharged state.

A dynamic random-access memory (DRAM) comprising:

• an array of bit cells, each bit cell having a corresponding access transistor coupled to a corresponding word line and a corresponding bit line, a corresponding storage transistor having a gate electrode coupled to a first current electrode of the corresponding access transistor, and a corresponding capacitor having a first terminal coupled to the gate electrode of the storage transistor, wherein:
• the corresponding access transistor of each bit cell is implemented as a high-voltage device and the corresponding select transistor of each bit cell is implemented as a low-voltage device wherein any two terminals of the high-voltage device can handle a higher voltage differential without damage as compared to the low-voltage device;
• and
• a controller configured to convert a selected bit cell of the array of bit cells to one-time-programmable (OTP) memory by turning on the corresponding access transistor of the selected bit cell and applying a voltage differential between the corresponding bit line and the corresponding voltage supply node sufficient to permanently break down a dielectric of the corresponding capacitor.