String zero/one full circle drain-side select gate over program countermeasure

A controller in communication with a memory apparatus including drain-side select gate transistors for coupling to a drain-side of each of a plurality of memory holes of memory cells and configured to retain a transistor threshold voltage, the plurality of memory holes arranged in rows comprising each of a plurality of strings, the controller configured to:

• instruct the memory apparatus to erase and program the transistor threshold voltage of the drain-side select gate transistors of the plurality of memory holes associated with one of the plurality of strings in one of a plurality of combined erase program operations for the one of the plurality of strings, each of the plurality of combined erase program operations including an erase portion and a first program portion and a second program portion;
• and
• in response to a string counter not equaling a total quantity of the plurality of strings, increment the string counter and instruct the memory apparatus to erase and program the transistor threshold voltage of the drain-side select gate transistors of the plurality of memory holes associated with another of the plurality of strings in another of the plurality of combined erase program operations for the another of the plurality of strings.

A method of operating a memory apparatus including drain-side select gate transistors for coupling to a drain-side of each of a plurality of memory holes of memory cells and configured to retain a transistor threshold voltage, the plurality of memory holes arranged in rows comprising each of a plurality of strings, the method comprising the steps of:

• erasing and programming the transistor threshold voltage of the drain-side select gate transistors of the plurality of memory holes associated with one of the plurality of strings in one of a plurality of combined erase program operations for the one of the plurality of strings, each of the plurality of combined erase program operations including an erase portion and a first program portion and a second program portion;
• and
• in response to a string counter not equaling a total quantity of the plurality of strings, incrementing the string counter and erasing and programming the transistor threshold voltage of the drain-side select gate transistors of the plurality of memory holes associated with another of the plurality of strings in another of the plurality of combined erase program operations for the another of the plurality of strings.