Three-dimensional one time programmable memory

A memory array comprising:

• a first set of one-time programmable (OTP) cells connected between a first program control line and a first read control line, wherein each OTP cell of the first set of OTP cells includes a programmable storage device and a switch connected between the first program control line and the first read control line, wherein the first program control line extends towards a first side of the memory array along a first direction, and wherein the first read control line extends along the first direction towards a second side of the memory array facing away from the first side of the memory array;
• and
• a second set of OTP cells connected between a second program control line and a second read control line, wherein each OTP cell of the second set of OTP cells includes a programmable storage device and a switch connected between the second program control line and the second read control line, wherein the second program control line extends towards the first side of the memory array, and wherein the second read control line extends towards the second side of the memory array;
• wherein each switch of the first set of OTP cells includes a gate electrode coupled to a gate electrode of a corresponding switch of the second set of OTP cells through a corresponding bit line extending along a second direction that is perpendicular to the first direction.

A memory array comprising:

• a first set of one-time programmable (OTP) cells connected between a first program control line and a first read control line, wherein each OTP cell of the first set of OTP cells includes a programmable storage device and a switch connected between the first program control line and the first read control line, wherein the first program control line extends towards a first side of the memory array along a first direction, and wherein the first read control line extends along the first direction towards a second side of the memory array facing away from the first side of the memory array;
• and
• a second set of OTP cells connected between a second program control line and a second read control line;
• wherein each switch of the first set of OTP cells includes a gate electrode coupled to a gate electrode of a corresponding switch of the second set of OTP cells through a corresponding bit line extending along a second direction that is perpendicular to the first direction.