Semiconductor memory device

A semiconductor storage device comprising:

• a memory string including a plurality of memory transistors connected in series;
• a power supply terminal that receives an operation voltage of the semiconductor storage device;
• a plurality of word lines connected to gates of the memory transistors, respectively;
• and
• a control circuit configured to:
• in response to a first command set, perform a first read operation;
• and
• in response to a second command set received during the first read operation, perform a second read operation after the first read operation, wherein
• during the first read operation, a voltage of a first selected one of the word lines with which data is to be read is decreased from a read pass voltage to a first read voltage at a first timing, and then increased to the read pass voltage at a second timing later than the first timing,
• during the second read operation, a voltage of a second selected one of the word lines with which data is to be read is set to a second read voltage at a third timing later than the second timing, and then increased to the read pass voltage at a fourth timing later than the third timing,
• a first current, which is a maximum current that flows through the power supply terminal during a first time period, is greater than a second current, which is a maximum current that flows through the power supply terminal during a second time period, and
• the first time period starts at a reception of the first command set and ends at the first timing, and the second time period starts the first timing and ends at the fourth timing.