Driver integrated circuit

A driver integrated circuit of a display panel, comprising:

• a source driver coupled to the display panel;
• and
• a controller coupled to the source driver and configured to output a plurality of gate clock signals to a gate driver according to a horizontal synchronous signal, wherein the gate driver is coupled to the display panel through a plurality of gate lines,
• wherein the horizontal synchronous signal is generated according to at least one table, and the at least one table records K time intervals of the horizontal synchronous signal for K gate lines of the plurality of gate lines,
• wherein an average time length of the K time intervals corresponds to an ideal scan time of the display panel.

A driver integrated circuit of a display panel, comprising:

• a source driver coupled to the display panel;
• and
• a controller coupled to the source driver and configured to output a first gate clock signal and a second gate clock signal to a gate driver according to a horizontal synchronous signal, wherein the gate driver is coupled to the display panel through a first gate line and a second gate line,
• wherein a first time length of a first time interval of the first gate clock signal is different from a second time length of a second time interval of the second gate clock signal according to the horizontal synchronous signal which is determined by accumulation errors of the first gate line and the second gate line.

A driver integrated circuit of a display panel, comprising:

• a source driver coupled to the display panel;
• and
• a controller coupled to the source driver and configured to output a gate clock signal to a gate driver according to a horizontal synchronous signal, wherein the gate driver is coupled to the display panel through a plurality of gate lines,
• wherein a first time length of a first time interval of the gate clock signal is different from a second time length of a second time interval of the gate clock signal according to the horizontal synchronous signal which is determined by accumulation errors of the plurality of gate lines.