An integrated circuit design and manufacturing system for optimized generation of a multi-core and/or multi-processor integrated circuit architecture or layout, integrated circuit performance, and integrated circuit manufacturing yield, the multi-core and/or multi-processor integrated circuit having a plurality of processing units and/or processing pipelines simultaneously processing instructions on data by executing a parallelized processing machine code,
- wherein the execution of the parallelized processing code by the parallel processing multi-core and/or multi-processor integrated circuit comprises the occurrence of latency times, the latency times being given by idle time of a processing unit from among the plurality of processing units between transmitting data back after having processed a specific block of instructions of the processing code on the data by the processing unit and receiving data necessary for execution of a consecutive block of instructions of the processing code by the processing units,
- the IC design and manufacturing system comprising:
- an auto-parallelization compiler system having processing circuitry configured to transform a serial source code of the program code written in a programming language into the parallelized processing machine code comprising a number of instructions executable by the plurality of processing units of the multi-core and/or multi-processor integrated circuit or control the operation of the plurality of processing units, combined with an IC-layout system for to generate a parallel processing IC layout with a plurality of integrated circuit layout elements at least comprising elements denoting memory units and elements denoting processing units and/or processing pipelines,
- wherein the compiler system comprises a parser module configured to translate the serial source code into a code with a flow of elementary instructions executable by the processing units, the elementary instructions selectable out of a limited, processing-unit-specific set of elementary instructions and the elementary instructions comprising exclusively elementary arithmetic and logic operations and/or elementary control and memory operations for the number of processing units,
- wherein the parser module comprises is further configured to partition the code of the elementary instructions into computation block nodes, each computation block node consisting of a smallest possible segmentation of a non-further decomposable sequence of elementary instructions of the code processable by the processing unit, the smallest possible segmentation of the elementary instructions being characterized by a sequence of elementary instructions framed by consecutive read and write instructions, the sequence being not further decomposable by smaller sequences of elementary instructions between consecutive read and write instructions, and the read and write instructions needed to receive data required for processing the sequence of elementary instructions by the processing unit and transmit back data after processing by the sequence,
- wherein the compiler system comprises a matrix builder configured to generate matrices out of computation chains portioned from the code, the matrices comprising computation matrices and transfer matrices and task matrices, wherein each column within a computation matrix comprises computation block nodes being simultaneously processable based on executability of read and write instructions transferring data required for processing of the computation block nodes, wherein the transfer matrix contains to each computation block nodes transfer and process properties at least characterizing data transfer properties from one to a consecutive computation block node at least comprising data size of transmitted data and identification of a source computation block node and target computation block node of the data transfer and/or process characteristics on one of the plurality of processing units,
- wherein tasks of a task matrix are formed by the matrix builder wherein in case of computation block nodes each having a different read associated, the tasks are formed by splitting the computation block nodes of a column of the computation matrix evenly to the number of the plurality processing units, which are symmetric, forming for each of the plurality of processing units per column of the computation matrix one task, and splitting remaining computation block nodes based on a predefined scheme to at least a part of the tasks, wherein in case of computation block nodes at least partially having a read with identical data transferred, the tasks are formed by minimizing the number of reads uniformly or essentially uniformly over the number of processing units and/or if a predefined offset value is exceeded by minimizing an integrated processing time uniformly over each of the processing units,
- wherein the compiler system comprises an optimizer module configured to use a matrix optimization technique minimizing an aggregated occurring latency time integrating all occurring latency times, wherein to provide an optimized structure of the tasks within the task matrix different combinations of rows from the computation and the transfer matrices are built by the optimizer module, each of the different combinations of rows from the computation and the transfer matrices representing a possible machine code as the parallelized processing machine code providing its properties on the hardware of the parallel processing system, wherein each column of the task matrix forms a computation chain by one or more tasks creating an ordered flow of computation block nodes to be executed by one of the plurality of processing units, and wherein the aggregated occurring latency time integrating all occurring latency times is minimized by the optimizer module,
- wherein the compiler system comprises a code generator configured to generate the parallelized processing machine code for the plurality of processing units with an optimized aggregated latency time based on the computation chains given by the optimized task matrix,
- wherein the IC-layout system comprises a netlist generator configured to generate a layout netlist being composed of a plurality of integrated circuit layout elements of an integrated circuit, the integrated circuit layout elements comprising electronic components of the integrated circuit at least comprising transistors, resistors, capacitors and interconnections of these components onto a piece of semiconductor,
- wherein a generated layout netlist comprise a plurality of parallel pipelines, each pipeline comprising an input latch and a processing circuit, wherein each input latch comprises the integrated circuit layout elements for a buffer or register, and a processing circuit comprises integrated circuit layout elements for processing the data of an associated input latch by a set of basic set of elementary instructions,
- wherein a processing stage is given by a particular data processing by one of the plurality of parallel pipelines producing an intermediate result, wherein the input latch and the processing circuit of a given stage is connected to the input latch of a next stage,
- wherein a clock signal is connected to each input latch, wherein a clock signal comprises the integrated circuit layout elements for generating a clock pulse, wherein at each clock pulse each of the plurality of parallel stages transfers an intermediate result to the input latches of the next stages, and wherein input data are passed through the plurality of parallel pipelines completing one stage per clock pulse until a final result is reached by completing all stages, and
- wherein the number of the plurality of parallel pipelines of a generated layout netlist corresponds to the maximal number of computation chains given by the optimized task matrix, wherein the layout netlist comprises a plurality of position variables generated and allocated to a plurality of layout elements by the netlist generator, wherein position variables represent the location of edges or points of the plurality of layout elements, and wherein an IC layout is generated by the netlist generator from the position variable values of the generated layout netlist.