Multi-cluster architecture for a hardware integrated circuit
AssigneeGoogle Inc.
InventorsSuyog Gupta, Ravi Narayanaswami, Hongil Yoon, Alekhya Perugupalli, Bhuvana Kurady Bairy, JiHong Min, Temitayo Fadelu
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AssigneeGoogle Inc.
InventorsSuyog Gupta, Ravi Narayanaswami, Hongil Yoon, Alekhya Perugupalli, Bhuvana Kurady Bairy, JiHong Min, Temitayo Fadelu
Estimating the term…
Methods and systems, including computer-readable media, are described for implementing a multi-cluster architecture for a hardware machine-learning (ML) accelerator. The architecture is implemented as a hardware integrated circuit and includes a controller that communicates with one or more cores and a first and second cluster of compute tiles. Each of the first and second cluster of compute tiles is configured to execute a respective ML workload. A first workload can be assigned to the first cluster of compute tiles and a second, different workload can be assigned to the second cluster of compute tiles. The first and second workloads are executed concurrently using the first and second clusters based on a program context of at least one core that is coupled to compute tiles of the first and second cluster.
An integrated circuit comprising:
A method performed using an integrated circuit comprising a controller, a first cluster comprising a first plurality of compute tiles, and a second cluster comprising a second plurality of compute tiles, the method comprising:
-40. (canceled)
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