Small outline transistor with thermal flat lead

A method of fabricating an electronic device, the method comprising:

• attaching a semiconductor die to a die attach pad of a given unit region of a lead frame panel array having rows and columns of unit regions, each unit region including a die attach pad with opposite ends, two tie bars connected to each end of the die attach pad along a column direction, and a lead;
• electrically connecting a circuit of the semiconductor die to the lead of the given unit region;
• performing a molding process that forms molded structures enclosing portions of the unit regions along the columns and exposing bottom sides of the die attach pads of the unit regions;
• and
• separating packaged electronic devices from the lead frame panel array to expose cut ends of the two tie bars along opposite cut ends of a package structure.

A method of fabricating a lead frame panel array, comprising:

• arranging unit regions in rows along a first direction and columns along an orthogonal second direction, each unit region including a die attach pad with opposite ends and opposite first and second sides, two tie bars connected to each end of the die attach pad along a column direction, and a lead;
• joining together the two tie bars of neighboring unit region;
• and
• spacing a first portion of the lead from a plane of the first side of the die attach pad, and a second portion of the lead having a bottom along the plane of the first side of the die attach pad.