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US 2026/0293672 A1Published application
Semiconductor package including heat dissipation layers
AssigneeSamsung Electronics Co., Ltd.
InventorsSeunghyun CHO, Jae-Min JUNG
Life of this patent
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Abstract
A semiconductor package includes a flexible insulating substrate including a first surface and a second surface opposite to the first surface, a first wiring on the first surface of the flexible insulating substrate, a second wiring on the second surface of the flexible insulating substrate, a plurality of vias coupling the first wiring to the second wiring, a plurality of semiconductor devices on the first surface of the flexible insulating substrate, and a heat dissipation resin layer at least partially covering at least one semiconductor device of the plurality of semiconductor devices.
Claims20
A semiconductor package, comprising:
- a flexible insulating substrate comprising a first surface and a second surface opposite to the first surface;
- a first wiring on the first surface of the flexible insulating substrate;
- a plurality of semiconductor devices on the first surface of the flexible insulating substrate;
- a heat dissipation resin layer at least partially covering at least one semiconductor device of the plurality of semiconductor devices;
- and
- a lower heat dissipation layer on the second surface of the flexible insulating substrate.
3 more elements
A semiconductor package, comprising:
- a flexible insulating substrate comprising a first surface and a second surface opposite to the first surface;
- a first wiring on the first surface of the flexible insulating substrate;
- a second wiring on the second surface of the flexible insulating substrate;
- a plurality of vias coupling the first wiring to the second wiring;
- a plurality of semiconductor devices on the first surface of the flexible insulating substrate;
- a plurality of solder bumps disposed between the plurality of semiconductor devices and the first wiring;
- a first solder resist at least partially covering at least a first portion of the first wiring;
- a second solder resist at least partially covering at least a second portion of the second wiring;
- a heat dissipation resin layer at least partially covering the plurality of semiconductor devices;
- and
- a lower heat dissipation layer coupled to the second solder resist,
- wherein the plurality of solder bumps comprises short-side-part solder bumps disposed along short sides of the plurality of semiconductor devices, and long-side-part solder bumps disposed along long sides of the plurality of semiconductor devices,
- wherein the short-side-part solder bumps are coupled to the second wiring using respective vias from among the plurality of vias, the respective vias being disposed directly below the short-side-part solder bumps, and
- wherein the heat dissipation resin layer comprises a thermally conductive polymer compound comprising a thermally conductive filler and at least one of an epoxy-based resin and a silicon-based thermosetting polymer.
11 more elements
A semiconductor package, comprising:
- a flexible insulating substrate comprising a first surface and a second surface opposite to the first surface;
- a first wiring on the first surface of the flexible insulating substrate;
- a second wiring on the second surface of the flexible insulating substrate;
- a plurality of vias coupling the first wiring to the second wiring;
- a plurality of semiconductor devices on the first surface of the flexible insulating substrate;
- a plurality of solder bumps disposed between the plurality of semiconductor devices and the first wiring;
- a first solder resist at least partially covering at least a first portion of the first wiring;
- a second solder resist at least partially covering at least a second portion of the second wiring;
- a heat dissipation resin layer at least partially covering at least one semiconductor devices of the plurality of semiconductor devices;
- a metal tape at least partially covering remaining semiconductor devices of the plurality of semiconductor devices;
- and
- a lower heat dissipation layer coupled to the second solder resist,
- wherein the plurality of solder bumps comprises short-side-part solder bumps disposed along short sides of the plurality of semiconductor devices, and long-side-part solder bumps disposed along long sides of the plurality of semiconductor devices,
- wherein the short-side-part solder bumps are coupled to the second wiring using respective vias from among the plurality of vias, the respective vias being disposed directly below the short-side-part solder bumps, and
- wherein the heat dissipation resin layer comprises a thermally conductive polymer compound comprising a thermally conductive filler and at least one of an epoxy-based resin and a silicon-based thermosetting polymer.
12 more elements
Dependencies are inferred from the claim text.