Semiconductor chip and semiconductor package

A method for manufacturing a semiconductor package comprising:

• forming a semiconductor wafer comprising:
• a substrate having main regions and a scribe region between the main regions,
• at least one test wiring structure on the scribe region,
• a low dielectric layer surrounding a lower portion of the at least one test wiring structure,
• at least one test pad on the at least one test wiring structure, and
• a first insulating layer surrounding an upper portion of the at least one test wiring structure and covering the at least one test pad, the first insulating layer having a partial region separating the low dielectric layer in a lateral direction within the scribe region;
• performing an electrical test through the at least one test pad;
• forming a second insulating layer on the first insulating layer, the second insulating layer covering the at least one test pad;
• forming a recess having a lateral wall provided by the first insulating layer and the second insulating layer, and a bottom provided by the first insulating layer;
• and
• dicing the semiconductor wafer along a dividing lane, the dividing lane passing through the bottom of the recess, the partial region of the first insulating layer, and the substrate.

A method for manufacturing a semiconductor package comprising:

• forming a semiconductor wafer comprising:
• a first test wiring structure and a second test wiring structure spaced apart from each other in a lateral direction,
• a low dielectric layer comprising a first section on a lower portion of the first test wiring structure, and a second section on a lower portion of the second test wiring structure,
• at least one test pad on each of the first and second test wiring structures, and
• a first insulating layer on upper portions of the first and second test wiring structures,
• wherein the first section and the second section are spaced apart from each other by the first insulating layer;
• forming a second insulating layer on the first insulating layer and the at least one test pad;
• forming a recess extending downwardly from an upper surface of the second insulating layer between the first and second test wiring structures;
• and
• dicing the semiconductor wafer passing between the first section and the second section of the low dielectric layer.