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US 2026/0293219 A1Published application
Integrated circuits with self-aligned tub architecture
AssigneeIntel Foundry IP LLC
InventorsDan S. LAVRIC, YenTing CHIU, Mohit K. HARAN, Allen B. GARDINER, Leonard P. GULER, Andy Chih-Hung WEI, Tahir GHANI
Life of this patent
Estimating the term…
Abstract
Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to integrated circuits with self-aligned tub architectures. Other embodiments may be described or claimed.
Claims20
An integrated circuit structure, comprising:
- an n-channel metal oxide semiconductor (NMOS) transistor having a gate stack and comprising a first plurality of nano-ribbons;
- a p-channel metal oxide semiconductor (PMOS) transistor having a gate stack and comprising a second plurality of nano-ribbons;
- a first gate wall, a second gate wall, and a third gate wall, wherein the gate stack of the NMOS transistor is disposed between and is in contact with the first gate wall and the second gate wall, and the gate stack of the PMOS transistor is disposed between and is in contact with the second gate wall and the third gate wall;
- and
- a work function metal (WFM) layer or dipole layer coupled to the first plurality of nano-ribbons, wherein the WFM layer or dipole layer is in contact with the first gate wall and the second gate wall.
2 more elements
An integrated circuit structure, comprising:
- an n-channel metal oxide semiconductor (NMOS) transistor having a gate stack and comprising a first plurality of nano-ribbons;
- a p-channel metal oxide semiconductor (PMOS) transistor having a gate stack and comprising a second plurality of nano-ribbons;
- a first gate wall, a second gate wall, and a third gate wall, wherein the gate stack of the NMOS transistor is disposed between and is in contact with the first gate wall and the second gate wall, and the gate stack of the PMOS transistor is disposed between and is in contact with the second gate wall and the third gate wall;
- and
- a work function metal (WFM) layer or dipole layer coupled to the second plurality of nano-ribbons, wherein the WFM layer or dipole layer is in contact with the second gate wall and the third gate wall.
2 more elements
A computing device, comprising:
- a board;
- and
- a component coupled to the board, the component including an integrated circuit structure, comprising:
- an n-channel metal oxide semiconductor (NMOS) transistor having a gate stack and comprising a first plurality of nano-ribbons;
- a p-channel metal oxide semiconductor (PMOS) transistor having a gate stack and comprising a second plurality of nano-ribbons;
- a first gate wall, a second gate wall, and a third gate wall, wherein the gate stack of the NMOS transistor is disposed between and is in contact with the first gate wall and the second gate wall, and the gate stack of the PMOS transistor is disposed between and is in contact with the second gate wall and the third gate wall;
- and
- a work function metal (WFM) layer or dipole layer coupled to the first plurality of nano-ribbons, wherein the WFM layer or dipole layer is in contact with the first gate wall and the second gate wall, or a work function metal (WFM) layer or dipole layer coupled to the second plurality of nano-ribbons, wherein the WFM layer or dipole layer is in contact with the second gate wall and the third gate wall.
5 more elements
Dependencies are inferred from the claim text.