Transistor device with multi-layer channel structure

An integrated chip comprising:

• a gate layer;
• an insulator layer over the gate layer;
• a pair of source/drain electrodes over the insulator layer;
• a dielectric layer over the insulator layer and laterally between the pair of source/drain electrodes;
• a first channel layer including a pair of channel structures directly over the insulator layer and directly under the pair of source/drain electrodes, respectively, wherein the pair of channel structures comprise a first semiconductor having a first carrier concentration;
• a second channel layer directly over the insulator layer, directly under the dielectric layer, and laterally between the pair of channel structures, wherein the second channel layer comprises a second semiconductor having a second carrier concentration, different from the first carrier concentration;
• and
• a third channel layer directly over the second channel layer, directly under the dielectric layer, and directly between sidewalls of the second channel layer.

An integrated chip comprising:

• a gate electrode;
• an insulator layer on the gate electrode;
• a first channel layer and a second channel layer laterally spaced apart on the insulator layer;
• a first source/drain electrode on the first channel layer and a second source/drain electrode on the second channel layer;
• a third channel layer on the insulator layer and laterally between the first channel layer and the second channel layer;
• and
• a fourth channel layer on the third channel layer, laterally between the first channel layer and the second channel layer, and laterally spaced from the first channel layer and the second channel layer.