Semiconductor device and electronic system including the same

A semiconductor device comprising:

• a substrate;
• a gate stack structure including interlayer insulation layers and gate electrodes alternately stacked in a first direction perpendicular to a surface of the substrate;
• a channel structure including a core insulation layer extending in the first direction, and a channel layer located between the core insulation layer and the gate electrode and connected to the substrate, the channel structure penetrating the gate structure;
• and
• a multi-layered structure extending in the first direction and including a first layer located between the channel layer and the gate electrode, a second layer located between the first layer and the gate electrode, and a third layer located between the first layer and the second layer,
• wherein each of the first layer and the second layer includes a ferroelectric material or an antiferroelectric material, wherein the third layer includes at least one insulation layer, and
• wherein the at least one insulation layer includes a charge storage layer containing an oxide and passivation layers containing a nitride and located on inner surface and outer surface of the charge storage layer.

An electronic system comprising:

• a main substrate;
• a semiconductor device on the main substrate;
• and
• a controller electrically connected to the semiconductor device on the main substrate,
• wherein the semiconductor device includes:
• a peripheral circuit region,
• a cell region including an input/output connection wiring electrically connected to the peripheral circuit region, and
• an input/output pad electrically connected to the input/output connection wiring extending into the cell region,
• wherein the cell region includes:
• a substrate,
• a gate stack structure including interlayer insulation layers and gate electrodes alternately stacked on the substrate,
• a channel structure including a channel layer extending in a first direction perpendicular to a surface of the substrate and connected to the substrate, the channel structure penetrating the gate stack structure, and
• a multi-layered structure extending in the first direction and including a first layer located between the channel layer and the gate electrode, a second layer located between the first layer and the gate electrode, and a third layer located between the first layer and the second layer,
• wherein each of the first layer and the second layer includes a ferroelectric material or an antiferroelectric material, and the third layer includes at least one insulation layer.