US 2026/0293089 A1 · MEMORY CELL CAPACITOR STRUCTURES FOR THREE-DIMENSIONAL MEMORY ARRAYS

Abstract

A memory device may include a memory array including multiple levels of memory cells that are each separated from another level by a respective dielectric layer. A memory cell at a first level of the memory array may include a channel portion and a capacitor operable to store a logic state of the memory cell. A first portion of the capacitor may be located between the channel portion and a voltage source coupled with the memory cell. A second portion of the capacitor may be in a cavity in a dielectric layer between the first level and a second level of the memory array. The second portion of the capacitor may be located between the channel portion and a word line coupled with a channel portion of a second memory cell at the second level.

Claims20

Dependent claims

An apparatus, comprising:

a digit line extending along a first direction;
and
a plurality of memory cells arranged along the first direction, wherein each memory cell of the plurality of memory cells comprises:
a respective cell selection component comprising a channel material electrically coupled with the digit line and extending along a second direction from the digit line;
and
a respective capacitor configured for electrical coupling with the digit line via the respective cell selection component, the respective capacitor comprising a first conductive plate having a first portion in contact with an end of the channel material of the respective cell selection component opposite the digit line, and having a second portion that extends from the first portion toward the digit line along the second direction.

3 more elements

Dependencies are inferred from the claim text.

Memory cell capacitor structures for three-dimensional memory arrays

Life of this patent

Memory cell capacitor structures for three-dimensional memory arrays

Life of this patent

Abstract

Claims20