Method and system for detecting fault injection attacks in a digital signature

A method for detecting fault injection attacks in a digital signature scheme, the method comprising:

• initiating a first counter configured to count a number of generations of digital signature candidates;
• initiating a second counter configured to count a number of digital signature candidates which fail security checks;
• generating a plurality of digital signature candidates and incrementing the first counter each time that a digital signature candidate is generated;
• selecting a size β and parsing the first counter in block intervals of said size β;
• performing security checks on each digital signature candidate generated,
• incrementing the second counter for each digital signature candidate which failed at least one security check;
• in response to the number of the first counter being an integer multiple of β:
• assigning a third counter to a last completed block interval of said size β, such third counter being configured to count a number of failed security checks in the last completed block interval;
• comparing the third counter with a criterion based at least on a probabilistic threshold and on said size β;
• and
• in response to the third counter not fulfilling the criterion:
• detecting that at least one fault injection attack has been performed.

A system for detecting fault injection attacks in a digital signature scheme, the system comprising:

• a digital signature generation unit configured to generate a plurality of digital signature candidates,
• a controller configured to perform at least one security check on each digital signature candidate created;
• and
• a processor configured to:
• initiate a first counter configured to count a number of generations of digital signature candidates;
• initiate a second counter configured to count a number of digital signature candidates which fail security checks;
• increment the first counter each time that a digital signature candidate is generated;
• parse the first counter in block intervals of a size J;
• and
• increment the second counter in response to a digital signature candidate failing at least one security check;
• a communication bus configured to communicatively couple the controller, the digital signature generation unit, and the processor;
• wherein the processor is further configured to:
• detect if the number of the first counter is an integer multiple of β;
• and in response to such detection:
• assign to a last completed block interval of the size β a third counter, such third counter configured to count a number of failed security checks registered in the last completed block interval;
• compare the third counter with a criterion based at least on a probabilistic threshold and on said size β;
• and
• in response to the third counter not fulfilling the criterion, detect that at least one fault injection attack has been performed.