Clock output apparatus having phase detection and calibration mechanism

A clock output apparatus having a phase detection and calibration mechanism, comprising:

• a clock output circuit configured to operate in a first mode and a second mode in turn to generate a pair of output clock signals, wherein the pair of output clock signals have a predetermined phase relation in the first mode;
• and
• a phase detection circuit comprising:
• a cross-coupled pair circuit electrically coupled between a power voltage and two output terminals;
• a differential input pair circuit;
• a determining circuit electrically coupled between the two output terminals and a ground voltage and having two input terminals configured to receive the pair of output clock signals, wherein the cross-coupled pair circuit and the differential input pair circuit operate together to generate two output signals at the two output terminals each having a level in a predetermined range around a center that is a half of the power voltage when the output clock signals are in phase and generate the two output signals at the two output terminals each having the level that is not in the predetermined range when the output clock signals are out of phase;
• and
• a determining circuit configured to receive at least one of the two output signals from the two output terminals to generate a phase determining result;
• wherein the clock output circuit performs a phase calibration process when the clock output circuit returns to the first mode from the second mode and the phase determining result indicates that the pair of output clock signals do not have the predetermined phase relation, so as to control the pair of output clock signals to have the predetermined phase relation.