Flip-flop circuit with selective clock gating

A method of operating a flip-flop circuit, comprising:

• receiving input data at a master latch;
• generating a master feedback node signal based on stored input data;
• generating an internal gated clock signal based on the master feedback node signal and a clock signal;
• disabling the internal gated clock signal when the master feedback node signal indicates storage of zero values;
• and
• maintaining a state of a slave latch when the internal gated clock signal is disabled.

A digital circuit system, comprising:

• a flip-flop circuit comprising:
• a master latch configured to:
• store input data;
• and
• generate a master feedback node signal indicating a stored data state;
• an integrated clock gating circuit configured to:
• receive the master feedback node signal and a clock signal;
• generate an internal gated clock signal based on the master feedback node signal and the clock signal;
• and
• disable the internal gated clock signal during consecutive clock cycles when the master feedback node signal indicates storage of zero values;
• and
• a slave latch configured to:
• receive the internal gated clock signal;
• and
• maintain a current output state when the internal gated clock signal is disabled.