Multiplexer layout and control in 3d-dram

An apparatus comprising:

• a word line extending in a first direction;
• a plurality of local digit lines extending in a second direction orthogonal to the first direction;
• a plurality of memory cells disposed at the intersections of the word line and the plurality of local digit lines;
• a plurality of global digit lines extending a third direction orthogonal to the first and the second direction;
• a plurality of multiplexer circuits, each configured to selectively couple one of plurality of local digit lines to a respective one of the plurality of global digit lines responsive to a multiplexer control signal;
• and
• a multiplexer driver configured to provide the multiplexer control signal, wherein the multiplexer driver is positioned above at least some of the plurality of memory cells in the second direction.

An apparatus comprising:

• a first 3D memory array patch comprising:
• a first plurality of memory cells disposed at the intersections of a plurality of word lines extending in a first direction and a first plurality of local digit lines extending in a second direction orthogonal to the first direction;
• a first plurality of global digit lines extending in a third direction orthogonal to the first and the second direction;
• and
• a first plurality of multiplexer circuits each configured to selectively couple a respective pair of the first plurality of local digit lines to an associated one of the first plurality of global digit lines;
• a second 3D memory array patch comprising:
• a second plurality of memory cells disposed at the intersection of the plurality of word lines and a second plurality of local digit lines extending in the second direction;
• a second plurality of global digit lines extending in the third direction;
• and
• a second plurality of multiplexer circuits each configured to selectively couple a respective pair of the second plurality of local digit lines to an associated one of the second plurality of global digit lines;
• a staircase region in between the first and the second 3D array patch;
• and
• a plurality of multiplexer drivers configured to provide multiplexer control signal to a respective set of multiplexers, wherein each of the respective sets of multiplexers includes a set of the plurality of first multiplexers and a set of the plurality of second multiplexers.