Memory system

A memory system comprising:

• a plurality of semiconductor memory devices;
• and
• a controller circuit,
• wherein each of the semiconductor memory devices includes
• a first signal pad to which a first signal is input,
• a second signal pad to which a second signal is input,
• a third signal pad to which a third signal is input,
• a fourth signal pad to which a fourth signal is input,
• a first input-output circuit configured to receive the second signal as command data or address data in response to toggling of the first signal,
• a second input-output circuit configured to output user data through the fourth signal pad in response to toggling of the third signal,
• a memory cell array including a plurality of memory cell transistors configured to store the user data, and
• a first switch circuit configured to connect the third signal pad and the first input-output circuit, wherein
• when the first switch circuit is on, the first input-output circuit receives the second signal and the third signal as command data or address data in response to the toggling of the first signal.

A method of transferring data between a plurality of semiconductor memory devices and a controller circuit, wherein each of the semiconductor memory devices includes

• a first signal pad to which a first signal is input,
• a second signal pad to which a second signal is input,
• a third signal pad to which a third signal is input,
• a fourth signal pad to which a fourth signal is input,
• a first input-output circuit configured to receive the second signal as command data or address data in response to toggling of the first signal,
• a second input-output circuit configured to output user data through the fourth signal pad in response to toggling of the third signal,
• a memory cell array including a plurality of memory cell transistors configured to store the user data,
• a first switch circuit configured to connect the third signal pad and the first input-output circuit,
• a decoding circuit configured to control the first switch circuit, and
• a sequencer including a feature register,
• said method comprising:
• controlling the first switch circuit in accordance with a control parameter stored in the feature register and a control signal output from the sequencer when the semiconductor memory device executes a data out operation of outputting the user data through the fourth signal pad, wherein
• when the first switch circuit is on, the first input-output circuit receives the second signal and the third signal as command data or address data in response to the toggling of the first signal.