Transistor
AssigneesSTMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS
InventorsSiddhartha DHAR, Stephane MONFRAY, Alain FLEURY, Franck JULIEN
Life of this patent
Estimating the term…
Abstract
A transistor includes a semiconductor layer with a stack of a gate insulator and a conductive gate on the semiconductor layer. A thickness of the gate insulator is variable in a length direction of the transistor. The gate insulator includes a first region having a first thickness below a central region of the conductive gate. The gate insulator further includes a second region having a second thickness, greater than the first thickness, below an edge region of conductive gate.
Claims19
A method for forming, in and on a semiconductor layer (11), a first transistor comprising a first gate insulator layer (132) having a first thickness (e4), a second transistor comprising a second gate insulator layer (131) of a second thickness (e3) greater than the first thickness (e4), and a third transistor comprising a third gate insulator layer (13) of variable thickness in a direction of a length (L) of the third transistor, the third gate insulation layer (13) comprising a first region having the first thickness (e4) opposite a central region of a conductive gate of the third transistor, and a second region having the second thickness (e3) facing edge regions of the conductive gate of the third transistor, the third gate insulator layer (13) having a step in thickness between the first and second regions, the process comprising the following successive steps:
- a) forming a first layer of gate insulation (131) having the second thickness (e3) on an upper surface of a semiconductor layer (11) opposite locations for the first, second and third transistors;
- b) locally removing the first layer of gate insulation (131) such that the surface of the semiconductor layer is exposed (11) opposite the location of the first transistor and a portion of the semiconductor layer is exposed at the first region of the location of the third transistor, said portion comprising a strip of width L1;
- c) forming a second layer of gate insulation (132) having the first thickness (e4) on the upper surface of the semiconductor layer at the location of the first transistor and at the portion of the semiconductor layer exposed in step b) at the first region of the location of the third transistor in the first region.
A method of manufacturing an integrated circuit including a first transistor having a first gate insulator with a first thickness, a second transistor having a gate insulator with a second thickness, and a third transistor having a gate insulator with a variable thickness along a length direction of the third transistor, wherein the second thickness is greater than the first thickness, and wherein the variable thickness comprises the second thickness below edge regions of a conductive gate for the third transistor and the first thickness at a location below a center of the conductive gate, the method comprising:
- forming a first gate insulator layer having the second thickness on an upper surface of a semiconductor layer at locations for the first, second and third transistors;
- locally removing the first gate insulator layer to expose the upper surface of the semiconductor layer at the location of the first transistor and at the location for the center of the conductive gate for the third transistor, while leaving the first gate insulator layer in place at locations for the edge regions of the conductive gate for the third transistor;
- forming a second gate insulator layer having the first thickness at the location of the first transistor and at the location for the center of the conductive gate for the third transistor;
- and
- forming, over the first and second gate insulator layers, conductive gates for the first, second and third transistors.
A method of manufacturing a transistor, comprising:
- forming a first gate insulator layer of thickness e3 on an upper surface of a semiconductor layer;
- locally removing the first gate insulator layer from a first region over a strip of width L1;
- forming a gate insulator layer of thickness e4 smaller than the thickness e3 on the upper surface of the semiconductor layer in the first region;
- and
- forming a conductive gate in front of a strip of width L, greater than width L1 and including said strip of width L1.
A method of manufacturing a transistor, comprising:
- depositing a gate insulator layer of a thickness e1 on an upper surface of a semiconductor layer;
- forming a conductive gate on top of and in contact with a portion of the gate insulator layer;
- and
- thermally oxidizing the gate insulator layer so that the gate insulator layer reaches a thickness e2, greater than the thickness e1, at locations below edge regions of the conductive gate and remains at the thickness e1 at a location below a center of the conductive gate.
Dependencies are inferred from the claim text.