Performance optimization by sizing gates and source/drain contacts differently for different transistors

A method of fabricating a semiconductor device, comprising:

• forming a patterned dummy gate electrode layer, wherein the patterned dummy gate electrode layer comprises a first segment having a first lateral dimension and a second segment having a second lateral dimension different than the first lateral dimension in value;
• replacing the patterned dummy gate electrode layer with a metal-containing gate electrode layer, wherein:
• the metal-containing gate electrode layer comprises a first metal-containing gate having the first lateral dimension and a second metal-containing gate having the second lateral dimension, and
• the first metal-containing gate is separated from the second metal-containing gate by an interlayer dielectric (ILD);
• etching a first source/drain contact opening in a first portion of the ILD adjacent to the first metal-containing gate and a second source/drain contact opening in a second portion of the ILD adjacent to the second metal-containing gate, wherein:
• the first source/drain contact opening is etched to have a third lateral dimension, and
• the second source/drain contact opening is etched to have a fourth lateral dimension different than the third lateral dimension in value;
• and
• filling the first source/drain contact opening and the second source/drain contact opening with a conductive material, thereby forming a first source/drain contact in the first source/drain contact opening and a second source/drain contact in the second source/drain contact opening.

A method of fabricating a semiconductor device, comprising:

• forming a first dummy gate electrode layer and a second dummy gate electrode layer;
• forming a first source/drain region adjacent the first dummy gate electrode layer and a second source/drain region adjacent the second dummy gate electrode layer;
• forming a first interlayer dielectric (ILD) structure over the first source/drain region and forming a second ILD structure over the second source/drain region;
• replacing the first dummy gate electrode layer with a first metal-containing gate electrode layer and replacing the second dummy gate electrode layer with a second metal-containing gate electrode layer;
• and
• etching the first ILD structure to define a first opening and etching the second ILD structure to define a second opening, wherein:
• a sidewall of the first ILD structure has a first lateral dimension, measured at a bottom surface of the first ILD structure from a surface of the first ILD structure defining the first opening to a surface of the first ILD structure facing the first metal-containing gate electrode layer,
• a sidewall of the second ILD structure has a second lateral dimension, measured at a bottom surface of the second ILD structure from a surface of the second ILD structure defining the second opening to a surface of the second ILD structure facing the second metal-containing gate electrode layer, and
• the second lateral dimension is different than the first lateral dimension.