High bandwidth memory system, method and device

A method of implementing a high bandwidth memory system, the method comprising:

• providing a substrate;
• coupling an interposer onto the substrate;
• electrically coupling a bottom of a dynamic random access memory (DRAM) stack onto the interposer;
• electrically coupling an application specific integrated circuit (ASIC) to a top of the DRAM stack;
• and
• electrically coupling a processing unit with the interposer such that the processing unit is positioned adjacent to the DRAM stack.

A high bandwidth memory system, the system comprising:

• means for supporting;
• means for interposing coupled with the means for supporting;
• means for providing a dynamic random access memory (DRAM) having a top and a bottom, wherein the bottom of the means for providing DRAM is electrically coupled with the means for interposing;
• application specific means for computing electrically coupled to the top of the means for providing DRAM;
• and
• means for processing positioned adjacent to the means for providing DRAM and electrically coupled with the means for interposing.

A high bandwidth memory system, the system comprising:

• a substrate;
• an application specific integrated circuit (ASIC) having a top and a bottom and including custom logic and control logic physically separated by a three-dimensional physical layer (3D PHY), wherein the 3D PHY includes a plurality of through silicon via (TSV) subfields separated by one or more gaps, and further wherein the custom logic is communicatively coupled with the control logic via routing components that extend through the gaps between the TSV subfields of the 3D PHY;
• an interposer electrically coupled with the substrate and the bottom of the ASIC;
• a dynamic random access memory (DRAM) stack electrically coupled with the top of the ASIC;
• and
• a processing unit positioned adjacent to the ASIC and the DRAM stack and electrically coupled with the interposer.