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US 2026/0282327 A1Published application
Thinned semiconductor device having doped semiconductive zone localized proximate to a memory array
AssigneeMicron Technology, Inc.
InventorsKamal M. KARDA, Durai Vishak Nirmal RAMASWAMY
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Abstract
Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, a semiconductor device assembly includes a memory array region, an insulative layer, an intrinsic semiconductive region between the memory array region and the insulative layer, and a doped semiconductive region that is contained within a lateral zone that is between the intrinsic semiconductive region and the insulative layer.
Claims20
A semiconductor device assembly, comprising:
- a memory array region;
- an insulative layer;
- an intrinsic semiconductive region between the memory array region and the insulative layer;
- and
- a doped semiconductive region that is contained within a lateral zone that is between the intrinsic semiconductive region and the insulative layer.
2 more elements
An apparatus, comprising:
- an integrated circuit region;
- a memory array region that is adjacent to the integrated circuit region;
- and
- a multi-layer semiconductor structure, comprising:
- a first level that spans the integrated circuit region and the memory array region, comprising:
- a first semiconductive layer that spans at least a portion of the integrated circuit region, and
- an insulative layer that spans at least a portion of the memory array region;
- a second level that spans the integrated circuit region and the memory array region, comprising:
- a second semiconductive layer that spans at least a portion of the integrated circuit region;
- and
- a doped semiconductive region that is contained within an approximately rectangular zone between the insulative layer and the memory array region.
8 more elements
A method, comprising:
- forming a multi-layer stack of semiconductive materials that includes a first level and a second level that spans the first level;
- forming, using the multi-layer stack, an integrated circuit region and a memory array region that is adjacent to the integrated circuit region and that includes active areas extending into the second level;
- joining a carrier to surfaces of the memory array region and the integrated circuit region;
- thinning the first level;
- forming, on a surface of the first level, a mask that spans the integrated circuit region;
- forming a recess in the first level;
- forming a doped semiconductive region that is localized at a base of the recess;
- and
- forming a dielectric layer in the recess and over the doped semiconductive region.
6 more elements
Dependencies are inferred from the claim text.