Memory device with back-gate transistor

A semiconductor structure, comprising:

• an interconnect structure disposed over a substrate and comprising a memory device including a transistor, wherein the transistor comprises:
• a gate region in at least one of a first metallization layer and a second metallization layer of the interconnect structure;
• a gate dielectric layer embedded in an isolation layer of the second metallization layer and over the gate region;
• a channel layer over the gate region;
• and
• two source/drain regions of the transistor over the channel layer on opposite sides of the gate region,
• wherein at least one of the gate region and the channel layer comprises two segments embedded in the isolation layer and parallel with each other, and
• wherein the two source/drain regions are embedded in the isolation layer and laterally surrounded by the isolation layer, and top surfaces of the two source/drain regions are substantially level with a top surface of the isolation layer.

A semiconductor structure, comprising:

• an interconnect structure disposed over a substrate and comprising a memory device including a transistor, wherein the transistor comprises:
• a gate region in a first metallization layer of the interconnect structure;
• a data storage layer embedded in a first isolation layer of a second metallization layer of the interconnect structure to cover a surface of the gate region exposed by the first isolation layer;
• a first channel layer embedded in the first isolation layer and on one side of the data storage layer opposite to the gate region;
• and
• two source/drain regions embedded in the first isolation layer,
• wherein the two source/drain regions are laterally surrounded by the first isolation layer, and top surfaces of the two source/drain regions are substantially level with a top surface of the first isolation layer and a top surface of the first channel layer.