Methods for operating a non-volatile memory array and a non-volatile memory cell for improving writing efficiency and erasing efficiency

A method for operating a non-volatile memory array that comprises a plurality of common-source lines arranged in parallel, a plurality of word lines arranged in parallel, a plurality of bit lines arranged in parallel, and a plurality of sub-memory arrays, the plurality of common-source lines comprise a first common-source line, the plurality of common-source lines are parallel to the plurality of word lines, the plurality of word lines comprise a first word line, the plurality of word lines are perpendicular to the plurality of bit lines, the plurality of bit lines comprise a first bit line, a second bit line, a third bit line, and a fourth bit line, each of the plurality of sub-memory arrays is coupled to one of the plurality of common-source lines, one of the plurality of word lines, and four of the plurality of bit lines, each of the plurality of sub-memory arrays comprises a first non-volatile memory cell, a second non-volatile memory cell, a third non-volatile memory cell, and a fourth non-volatile memory cell, the first non-volatile memory cell is coupled to the first word line, the first bit line, and the first common-source line, the second non-volatile memory cell is coupled to the first word line, the second bit line, and the first common-source line, the third non-volatile memory cell is coupled to the first word line, the third bit line, and the first common-source line, the fourth non-volatile memory cell is coupled to the first word line, the fourth bit line, and the first common-source line, each of the first non-volatile memory cell, the second non-volatile memory cell, the third non-volatile memory cell, and the fourth non-volatile memory cell comprises an N-type field-effect transistor (FET), the first non-volatile memory cell, the second non-volatile memory cell, the third non-volatile memory cell, or the fourth non-volatile memory cell is used as an operable memory cell, and the method comprises:

• applying a grounding voltage to a body of the N-type FET of the operable memory cell;
• and
• when the operable memory cell performs a writing activity or an erasing activity, respectively applying a bit voltage, a first word voltage, and a first common-source voltage to the bit line, the first word line, and the first common-source line that are coupled to the operable memory cell;
• wherein the N-type FET of the operable memory cell has a threshold voltage;
• wherein in the writing activity, the bit voltage is equal to a high voltage, the first word voltage increases incrementally in response to the threshold voltage that increases incrementally, and the first common-source voltage decreases incrementally in response to the threshold voltage that increases incrementally;
• wherein in the erasing activity, the bit voltage is equal to the high voltage, the first word voltage decreases incrementally in response to the threshold voltage that decreases incrementally, and the first common-source voltage is equal to the grounding voltage;
• wherein the high voltage is equal to a drain-to-source breakdown voltage of the N-type FET of the operable memory cell minus the threshold voltage.