Memory device and operating method of the memory device

A method of operating a memory device, the memory device comprising a normal memory cell for multiple programming, a one-time programmable (OTP) memory cell for one-time programming, a normal reference cell, an OTP reference cell, and a reference switching circuit, the method comprising:

• determining, based on a control signal received from a memory controller, that a read operation is a read operation of the normal memory cell or a read operation of the OTP memory cell;
• and
• based on determining that the read operation is the read operation of the normal memory cell, generating a first reference resistance value based on a resistive element of the reference switching circuit by turning off a switch transistor of the reference switching circuit;
• and
• based on determining that the read operation is the read operation of the OTP memory cell, generating a second reference resistance value (i) by turning on the switch transistor of the reference switching circuit and bypassing the resistive element of the reference switching circuit, and (ii) by combining a plurality of OTP reference cells,
• wherein the normal reference cell and the OTP reference cell are configured to share a target reference bit line and are connected to the reference switching circuit through the target reference bit line.

A memory system comprising:

• a memory controller;
• and
• a memory device comprising a cell array and a reference switching circuit, the cell array including a normal memory cell capable of multiple programming, a one-time programmable (OTP) memory cell capable of one-time programming, a normal reference cell, and an OTP reference cell, and the reference switching circuit connected to the cell array through a target reference bit line,
• wherein the normal reference cell and the OTP reference cell are configured to share the target reference bit line, and
• wherein the memory device is configured to:
• based on a read operation being a read operation of the normal memory cell, generate a first reference signal based on a resistive element of the reference switching circuit by using the target reference bit line;
• and
• based on the read operation being a read operation of the OTP memory cell, generate a second reference signal based on a switch transistor of the reference switching circuit and a variable resistance element of the OTP reference cell by using the target reference bit line.