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AssigneeIntel Corporation
InventorsSridhar Muthrasanallur, Debendra Das Sharma, Swadesh Choudhary, Gerald Pasdast, Peter Onufryk
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Technologies for a unified debug and test architecture in chiplets is disclosed. In an illustrative embodiment, several chiplets are integrated on an integrated circuit package. The chiplets are connected by a package interconnect, such as a universal chiplet interconnect express (UCIe) interconnect. Each chiplet includes several debug nodes, which are connected by an on-chiplet network. One of the chiplets, referred to as a package debug endpoint, acts as a link endpoint for an off-package link, such as a peripheral component interconnect express (PCIe) link. In use, debug messages can be sent to the package debug endpoint over a PCIe link. The debug messages can be routed within the chiplets and between chiplets, allowing for the debug functionality at each debug node to be probed using a common protocol. In this manner, chiplets from different vendors can be integrated into the same package and tested using common software.
1-20. (canceled)
A chiplet comprising:
An integrated circuit package comprising the chiplet of claim 1 and the other chiplet,
The integrated circuit package of claim 2, further comprising at least one debug hardware interface pinned out in the integrated circuit package.
The integrated circuit package of claim 2, wherein the chiplet is to:
The integrated circuit package of claim 4, wherein the first protocol is a peripheral component interconnect express (PCIe) protocol, and wherein the second protocol is a universal chiplet interconnect express (UCIe) protocol.
The chiplet of claim 1, further comprising a package debug endpoint, wherein the package debug endpoint comprises link endpoint circuitry to form an off-package link with a device, wherein the link endpoint circuitry is to form a peripheral component interconnect express (PCIe) link with the device, wherein the link endpoint circuitry is to form a universal chiplet interconnect express (UCIe) link with an other chiplet.
The chiplet of claim 1, wherein individual debug spokes of the plurality of debug spokes are assigned respective debug spoke identifiers that are unique within the chiplet, and wherein the debug hub is configured to route an individual debug message to a selected debug spoke of the plurality of debug spokes based on a debug spoke identifier in the individual debug message.
The chiplet of claim 1, wherein individual debug spokes of the plurality of debug spokes implement a standardized register set that supports register read accesses and register write accesses.
The chiplet of claim 8, wherein at least one debug spoke of the plurality of debug spokes includes a vendor-defined register space to trigger a built-in self test, read one or more internal debug registers, or provide an array dump.
The chiplet of claim 1, wherein the debug functionality of a first debug spoke of the plurality of debug spokes comprises a memory built-in self test.
The chiplet of claim 1, further comprising interface circuitry communicatively coupled to the debug hub, wherein the interface circuitry is configured to receive a debug message from off chiplet using at least one of a joint test action group (JTAG) interface, a general purpose input/output (GPIO) interface, a peripheral component interconnect express (PCIe) interface, a universal serial bus (USB) interface, a system management bus (SMBus) interface, an inter-integrated circuit (I2C) interface, or an improved inter-integrated circuit (I3C) interface.
An integrated circuit package comprising:
The integrated circuit package of claim 12, wherein the first debug message is in a packet compliant with a first protocol, and wherein the second debug message is in a packet compliant with a second protocol different from the first protocol.
The integrated circuit package of claim 12, wherein the debug spoke identifier is unique among a plurality of debug spoke identifiers for a plurality of debug spokes of the second chiplet.
The integrated circuit package of claim 12, wherein the second debug message comprises a vendor-defined universal chiplet interconnect express (UCIe) design for debug or design for test message that includes the debug spoke identifier.
The integrated circuit package of claim 12, wherein the package debug endpoint is to receive a response message from the second chiplet over the UCIe link and send, to the device external to the integrated circuit package, a completion debug message corresponding to the first debug message.
A method comprising:
The method of claim 17, wherein the first debug message is received through at least one of a joint test action group (JTAG) interface, a general purpose input/output (GPIO) interface, a peripheral component interconnect express (PCIe) interface, a universal serial bus (USB) interface, a system management bus (SMBus) interface, an inter-integrated circuit (I2C) interface, or an improved inter-integrated circuit (I3C) interface.
The method of claim 17, wherein performing the test or debug function comprises at least one of accessing a register of the debug spoke, executing a memory built-in self test, controlling scan circuitry, or reporting a status of the chiplet.
The method of claim 17, further comprising:
Dependencies are inferred from the claim text.