Cmos image sensor

An image sensor, comprising:

• a first integrated circuit die comprising transistors disposed on a first substrate and first interconnects formed in a first plurality of wiring layers formed over the first substrate;
• and
• a second integrated circuit die comprising photodiodes disposed on a second substrate and second interconnects formed in a second plurality of wiring layers formed over the second substrate,
• wherein:
• the second integrated circuit die is stacked over and electrically connected to the first integrated circuit die with electrical connections formed between the first interconnects and the second interconnects;
• the photodiodes of the second integrated circuit die comprise first photodiodes in an image pixel area and at least one second photodiode configured to determine a dark voltage current in a black level calibration area;
• the second integrated circuit die further comprises a first seal ring and a second seal ring surrounding the image pixel area in a plan view, such that the at least one second photodiode is disposed between the first seal ring and the second seal ring;
• and
• the first seal ring and the second seal ring comprise conductive wiring patterns and conductive vias coupling adjacent wiring patterns.

An image sensor, comprising:

• a substrate;
• an image pixel area of the substrate comprising a plurality of first photodiodes;
• a black level calibration area of the substrate comprising at least one second photodiode configured to determine a dark voltage current;
• a first seal ring disposed over the substrate and surrounding the image pixel area in a plan view;
• a second seal ring disposed over the substrate and surrounding the image pixel area in the plan view, such that the at least one second photodiode is disposed between the first seal ring and the second seal ring;
• a first barrier structure disposed in the substrate over the first seal ring;
• and
• a second barrier structure disposed in the substrate over the second seal ring,
• wherein:
• the at least one second photodiode is disposed between the first barrier structure and the second barrier structure in the plan view;
• and
• the first seal ring and the second seal ring comprise conductive wiring patterns and conductive vias coupling adjacent wiring patterns.