Multiphase voltage regulation circuit having interleaved clock control mechanism

A multiphase voltage regulation circuit having an interleaved clock control

• mechanism, comprising:
• a plurality of voltage regulators;
• and
• a clock signal generator circuit connected to the plurality of voltage regulators;
• wherein the clock signal generator circuit is configured to:
• use a frequency of a pulse wave of a target clock signal as a target frequency;
• multiply the target frequency by a number of the plurality of voltage regulators to obtain a reference frequency;
• generate a reference clock signal based on the reference frequency, wherein a frequency of each of a plurality of pulse waves of the reference clock signal is equal to the reference frequency;
• and
• divide the reference clock signal into a plurality of regulation clock signals and output the plurality of regulation clock signals respectively to the plurality of voltage regulators, wherein a frequency of each of a plurality of pulse waves of the plurality of regulation clock signals is equal to the target frequency, and a plurality of phases of the plurality of pulse waves of each one of the plurality of regulation clock signals are respectively not overlapped with that of another of the plurality of regulation clock signals;
• wherein each of the plurality of voltage regulators is configured to obtain an input voltage from an input power source based on the regulation clock signal, and configured to modulate the input voltage into an output voltage.