In-system on-chip memory repair for safety critical applications and automotive design

An apparatus, comprising:

• a memory of a vehicle storing processor-readable code;
• and
• one or more processors coupled to the memory, the one or more processors configured to execute the processor-readable code to cause the one or more processors to:
• determine, for the memory of the vehicle, whether units of the memory fail a memory function test;
• determine whether one or more units of the memory that fail the memory function test are repairable;
• and
• adjust, during operation of the vehicle, access to at least one unit of the memory that fails the memory function test and is repairable.

A system for an in-field memory repair in a vehicle, comprising:

• a memory of the vehicle, wherein the memory comprises a plurality of units and stores processor-readable code;
• and
• at least one processor coupled to the memory, wherein the at least one processor is configured to execute the processor-readable code to cause the at least one processor to perform operations comprising:
• determining, for each unit of the memory via a memory built-in self test (MBIST) vector, whether each unit fails a memory function test;
• determining, via a built-in redundancy analysis (BIRA) vector, based on a memory repair history of the memory, whether one or more units of the memory that fail the memory function test are repairable;
• adjusting, by enabling a built-in self repair (BISR) vector, access to at least one unit of the memory that fails the memory function test and is repairable without fusing any units of the memory;
• and
• confirming, via the MBIST vector, that the access to the at least one unit of the memory is successfully adjusted.