Memory device and method of reading memory device

Abstract

A memory device includes a memory cell array and a peripheral circuit. The memory cell array includes a plurality of strings coupled between a bit line and a source line and each of the plurality of strings comprises a drain selection transistor coupled to a corresponding drain selection line, memory cells coupled to a plurality of word lines, and a source selection transistor coupled to a corresponding source selection line. The peripheral circuit is configured to apply a subthreshold gate voltage to a particular source selection line coupled to an unselected string among the plurality of strings, while applying a turn-off voltage to a particular drain selection line coupled to the unselected string, during at least a portion of a read interval in which a read pass voltage is applied to unselected word lines among the plurality of word lines.

Dependencies are inferred from the claim text.